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| 74ACT32701 16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED) PRELIMINARY DATA s s s s s s s s s HIGH SPEED: tPD = 4.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8A(MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V FUNCTION COMPATIBLE WITH SERIES 16373 AND 16245 (244) IMPROVED LATCH-UP IMMUNITY IMPROVED ESD IMMUNITY LFBGA96 (Top and Bottom view) ORDER CODES PACKAGE LFBGA96 TRAY 74ACT32701LB T&R 74ACT32701LBR DESCRIPTION The 74ACT16244 is a low voltage CMOS 16-BIT D-TYPE LATCH and 16 BIT BUS TRANSCEIVER with 3-STATE output non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Both functions can be used as 16 bit or dual octal devices, so the 16 bit transceiver can be used ad 8 bit bus buffer plus 8 bit transceiver, or only 16 bit buffer in select direction. LOGIC DIAGRAM This device can be used to integrate in one chip the internal logic component required to STV0701 to work ad P.O.D. interface in Digital TV application. It is ideal for low power and high speed 4.5 to 5.5. applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. July 2003 1/9 This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice. 74ACT32701 PIN CONNECTION (Top view) TERMINAL ASSIGNMENT A 6 5 4 3 2 1 1D2 1D1 1LE B 1D4 1D3 GND C 1D6 1D5 VCC VCC 1Q5 1Q6 D 1D8 1D7 E 2D2 2D1 F 2D4 2D3 VCC VCC 2Q3 2Q4 G 2D6 2D5 GND GND 2Q5 2Q6 H 2D7 2D8 2LE J 3A2 3A1 3G K 3A4 3A3 GND L 3A6 3A5 VCC VCC 3B5 3B6 M 3A8 3A7 N 4A2 4A1 P 4A4 4A3 VCC VCC 4B3 4B4 R 4A6 4A5 GND T 4A7 4A8 4G GND GND GND GND 1Q7 1Q8 2Q1 2Q2 GND GND GND GND 3B7 3B8 4B1 4B2 1OE GND 1Q1 1Q2 1Q3 1Q4 2OE 3DIR GND 2B8 2B7 3B1 3B2 3B3 3B4 GND 4DIR 4B5 4B6 4B8 4B7 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE (each 8bit section of 16bit Latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z TRUTH TABLE (each 8bit section of 16bit Transceiver) INPUTS OPERATION G L L H X : Don`t Care Z : High Impedance DIR L H X B data to A bus A data to B bus Isolation 2/9 74ACT32701 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 400 -65 to +150 300 Unit V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -40 to 85 8 Unit V V V C ns/V 1) VIN from 0.8V to 2.0V 3/9 74ACT32701 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II IOZ ICCT ICC IOLD IOHD Input Leakage Current High Impedance Output Leakage Current Max ICC/Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 A IO=-50 A IO=-24 mA IO=-24 mA IO=50 A IO=50 A IO=24 mA IO=24 mA VI = VCC or GND VI = VIH or VIIL VO = VCC or GND VI = VCC - 2.1V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min. 0.9 8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.5 4.49 5.49 Value TA = 25C Min. 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1 5 1 80 75 -75 A A mA A mA mA V Typ. Max. -40 to 85C Min. 2.0 2.0 0.8 0.8 V Max. V Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) Value TA = 25C Min. 2.0 3.0 4.0 3.0 4.0 3.0 Typ. 3.3 4.8 6.5 5.5 6.0 4.6 Max. 5.0 6.5 8.7 7.7 8.0 6.4 -40 to 85C Min. 2.0 3.0 4.0 3.0 4.0 3.0 Max. 6.0 8.0 9.7 8.8 9.2 7.3 ns ns ns Unit tPLH tPHL tPZL tPZH tPLZ tPHZ Propagation Delay Time Output Enable Time Output Disable Time (*) Voltage range is 5.0V 0.5V 4/9 74ACT32701 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 5.0 fIN = 10MHz Value TA = 25C Min. Typ. 3.6 11 42 Max. -40 to 85C Min. Max. pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) TEST CIRCUIT Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50) Switch Open 2VCC GND 5/9 74ACT32701 WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 6/9 74ACT32701 LFBGA96 MECHANICAL DAT A mm. DIM. MIN. A B C D E F 0.85 0.5 0.8 33.5 13.40 5.40 TYP MAX. 13.60 5.60 1.6 19.7 31.5 MIN. 527.5 212.6 TYP. MAX. 535.4 220.5 63.0 mils 7/9 74ACT32701 Tape & Reel LFBGA96 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 5.8 13.8 2.1 3.9 7.9 12.8 20.2 60 30.4 6.0 14.0 2.3 4.1 8.1 0.228 0.543 0.083 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 1.196 0.236 0.551 0.091 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 8/9 74ACT32701 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 9/9 |
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